What is an IGBT Fault Current Limiting Circuit?
IGBT fault current limiting circuits can extend the short-circuit withstand time of an IGBT by limiting the magnitude of the fault current. Simultaneously, this fault current limitation reduces the turn-off voltage transient and significantly reduces the negative Miller effect, a side effect that can be exploited, especially in higher-current modules. This structure is particularly suitable for noise-prone systems.
This circuit does not require an external DC power supply and, with its simple structure, can be integrated into the IGBT module or used as an interface between the gate driver and the module. This circuit operates by detecting faults and reducing the gate voltage. The reduced gate voltage limits the magnitude of the fault current and thus extends the short-circuit withstand time.
Operating Principle
In application, if the device experiences a sustained short circuit, the high current dissipation will cause a temperature rise. Due to its short time constant, the module temperature rises extremely rapidly. If the module temperature exceeds the silicon die's intrinsic temperature (250℃), the device loses its blocking capability, rendering gate-controlled protection ineffective. Reducing the fault current amplitude, however, limits the IGBT module's power dissipation, thereby extending the fault withstand time and potentially allowing the IGBT to operate for extended periods under short-circuit conditions.
Circuit Design
In the circuit shown in Figure 1, Zener diode VS1 generates the required clamping voltage. Fast diode VD1, with the same voltage rating as the protected IGBT, serves as the fault detection element. Diode VD2 blocks the negative off-state gate bias. Vl(MOSFET) controls the circuit's on/off state. Resistors RG, R1, R2, and R3 generate the required time constant t1, calculated as follows:
t1 = [(RG + R1 + R2)R3 / (RG + R1 + R2 + R3)] × Ciss
In the formula, Ciess is the MOSFET's input capacitance.
Figure 1 IGBT drive circuit with FCLC
This circuit uses collector-emitter voltage (VCE) sensing to detect short-circuit faults. While the IGBT remains in the off state, diode VD1 is reverse biased. The gate driver begins charging V1's gate at a rate determined by time constant T1. This time constant is adjusted to maintain V1's gate voltage below its threshold at least until the IGBT completes its turn-on process.
Under normal circuit conditions, the gate drive voltage is applied to the gate and emitter. When VCE exceeds the gate threshold, the IGBT begins conducting. At the end of the turn-on transient, VCE decreases to its on-state voltage drop. This process takes between 0.1 and 2μs (depending on the IGBT's characteristics and the load current magnitude).
If this turn-on process proceeds normally, VCE will decrease to its on-state voltage drop. When VCE falls below the gate signal level (e.g., 15V), diode VD1 becomes forward biased, and the potential at point a begins to decrease along with VCE. As the turn-on process nears completion, the voltage at point a drops to a few volts. In this case, resistors R1 and R2 are adjusted to keep the MOSFET gate voltage below its threshold level.
If an IGBT short-circuit occurs, when the supply voltage is applied across the collector and emitter, VCE remains at the off-state level. Diode VD1 remains reverse biased, and the MOSFET gate potential continues to rise toward a level determined by the gate voltage and the relative values of resistors R1, R2, and R3. These resistors prevent V1 from turning on in this situation. Once V1 is turned on, the IGBT gate signal is held at a low voltage, primarily determined by the avalanche voltage of Zener diode VS1.
By maintaining the gate voltage at a low level, the fault current amplitude is reduced, thereby reducing the power dissipation in the IGBT module. The most direct effect of reducing losses is an increase in the device's short-circuit withstand time. The FCLC (Frequency Limiting Circuit) reduces the fault current from 400A to 230A, while the energy dissipation is reduced from 1.35J to 0.8J within 10μs.
In applications where narrow, high-amplitude current spikes are common, such as capacitive currents in motor cables or noise-induced shoot-through transients, the level must be limited to reduce the gate voltage. If such transients are considered non-destructive, they must not adversely affect protection circuits that could cause system breakdown. Therefore, the clamping voltage must be maintained high enough to allow the circuit to pass without latching off. The clamping voltage value is determined by the estimated maximum load current for any given application. The IGBT gate voltage should be high enough to supply sufficient load current while the device is still in saturation. In real-world applications, the maximum load current can be significantly lower than the peak rated current, allowing the use of a much lower clamping voltage, thereby extending the short-circuit withstand time.
Faults can occur while the IGBT is in the on state, carrying inductive load current before the fault occurs. VCE rapidly rises from the low on-state voltage to the DC blocking voltage. The diode is reverse biased at this point; as in the previous case, the IGBT gate signal begins charging the MOSFET input capacitance, accelerated by the recovery current of diode VD1. Ultimately, the IGBT gate voltage is limited within a relatively short timeframe; this is a beneficial effect in this fault type, as it negates the need for delayed circuit response. In fact, faster circuit response helps reduce the undesirable Miller effect.
At the end of the fault, the IGBT current returns to the load current; VCE returns to the on-state voltage level; diode VD1 returns to forward bias; and the clamp circuit is turned off. The gate voltage returns to its initial value, and operation can continue unimpeded. If the gate clamp voltage drops too low, the IGBT will not be able to withstand the load current, and VCE will remain high even after the transient fault disappears. In this state, the FCLC will remain latched off, maintaining the IGBT in a "pseudo" fault state. This process ensures that the primary protection circuit is not falsely triggered and that the circuit is shut down. By selecting the appropriate clamp voltage, glitches that could cause protection to operate can be avoided. It can be seen that as the clamping gate voltage is reduced, the IGBT's short-circuit withstand time can be significantly extended, making the use of a slow primary protection circuit possible.
The circuit shown in Figure 2 eliminates the MOSFET selection issue. VS2 is used to offset the IGBT's on-state voltage drop (regardless of how high this voltage drop may be). In this way, even when the IGBT experiences the worst-case load current, the voltage at the VS1 gate remains below its gate threshold voltage, and the clamping circuit remains in the off state.
Figure 2: Improved IGBT Driver Circuit with FCLC
The circuit shown in Figure 3 is a second-order derivative of the FCLC, which gradually reduces the gate voltage to extend the short-circuit protection time. After the first stage, also known as the diagnostic stage, the gate voltage level is further reduced by the operation of V2. The time constant T2 for V2 triggering is determined by the values of R4, Rs, and C2; C2 is the sum of the MOSFET input capacitance and the external discrete capacitance.
Figure 3 IGBT drive circuit with a second-order derived FCLC
In some applications, it may be necessary to completely shut down the IGBT after the first diagnostic phase. This can be achieved by reducing the clamping voltage to a level below the IGBT gate threshold voltage. Simply by selecting the appropriate clamping voltage, the IGBT fault current can be controlled and the short-circuit withstand time can be extended. While maintaining normal IGBT operation, reducing the fault current significantly reduces silicon die losses, minimizes the likelihood of device latch-up, and reduces the magnitude of the turn-off overvoltage. If the fault current is transient, the circuit restores the gate signal and continues normal operation, consuming only a small amount of energy generated by the gate signal itself.
Technical Advantages
Extended withstand time: By limiting the current amplitude, the temperature rise is suppressed, preventing silicon die failure due to exceeding the intrinsic temperature (250℃).
Enhanced reliability: Significantly suppresses the Miller effect, reducing the risk of turn-off overvoltage and device latch-up.
Adaptive recovery: The circuit automatically resets after a transient fault, ensuring continuous system operation.
Low-power design: Consuming only the gate signal's own energy, no external power supply is required.
Application Scenarios
SHYSEMI FCLC technology is widely used in high-frequency, high-noise scenarios such as motor drives, frequency converters, and inverters. It provides critical protection for SHYSEMI IGBT drive circuits, significantly improving system robustness and meeting the protection requirements of industrial-grade SHYSEMI IGBT modules.